Nano silicon solar cells: How do solar panels work ? To answer this questi...

Nano silicon solar cells: How do solar panels work ?
 To answer this questi...: How do solar panels work ?    To answer this question all you have to do is watch this video..... Enjoy watching ....

Methods

Si-NW growth

Silicon nano-wires were synthesized in a two-step growth process via V LS mechanism. At first, the gallium layer of various thicknesses was deposited onto soda-lime glass and Si/SiO₂ substrates via thermal evaporation. SiO₂ layer of 1 nm thickness was used as a barrier to prevent possible diffusion of Ga into Si. The thickness of the Ga layer was varied between 7.5 and 100 nm.

The samples were then loaded into an RF-PECVD reactor with radio frequency of 13.56 MHz and left for 4 h. Hydrogen gas was introduced into the chamber, while the substrate, coated with Ga layer, is being heated up to the growth temperature. Prior to introduction of the precursor gas, hydrogen plasma was created for 5 min in order to remove possible contamination and gallium oxide layer from the substrate. Si-lane (SiH₄) was used as Si source. Gas flow rates, RF power, chamber pressure and deposition duration were process variables that have been investigated in detail and will be reported elsewhere.

Fabrication of bistable memory device

For the fabrication of a bistable memory device, glass substrate was used. Al contacts were deposited by thermal evaporation. Two silicon nitride (Si₃N₄) dielectric layers of 20 nm each were deposited in a PECVD system, sandwiching Si-NWs between the bottom and top electrodes. Si-NWs were grown for 30 min from 100-nm Ga catalyst layer at 400°C. After the Si₃N₄/Si-NW/Si₃N₄/Al/glass structure was fabricated, the second layer of Al contacts was evaporated to finalize the device. The device characteristics were tested by I-V and data retention time measurements.

Fabrication of Schlocky diode

Sin W-based Schlocky diodes were fabricated by growing the Si-NWs directly on glass substrate from 50 nm Ga at 400°C for 20 min with subsequent evaporation of both Al contacts on top of the nano-wires. The device characteristics were tested via I-V measurements.

Fabrication of solar cells

During solar cell fabrication, a glass substrate covered with transparent conductive oxide (TCO) layer (the details of the layer will be reported elsewhere) was utilized. Si-NWs were grown on top of this layer from 50 nm Ga at 400°C for 40 min. Nano-wires for the solar cell were grown using additional phosphine in the reaction chamber for n-type doping of the nano-wires. After the nano-wire growth Al dots were evaporated for top contact.

Background

Silicon nano-wires (Si-NWs) have attracted the attention of many researchers due to their structural, optical, electrical and thermoelectric properties. They are expected to be important building blocks in the future nano-electronic and phonic devices including solar cells, field-effect transistors, memory devices and chemical and biomedical sensors. Owing to their compatibility with the Si-base technology, Si-NWs can be used not only as the functional units of the devices but also as the interconnects .

Various methods have been reported for Si-NW fabrication, including both bottom-up and top-down techniques. Bottom-up growth methods include laser ablation, evaporation, solution-based methods and chemical vapor deposition (CVD). The CVD growth usually takes place via vapor-liquid-solid (VLS) route . Many catalyst materials, mainly metals including Au, Al, Ni, Fe and Ag, have been used for the Si-NW growth . Among these metals, Au as catalyst has been the most popular and most widely investigated due to its chemical inertness and low eutectic temperature of Au-Si system. However, Au introduces deep impurity levels in Si band-gap and degrades the charge carrier mobility . Therefore, alternative catalyst investigation is of crucial importance.

One of the important parameters when considering the nano-wire fabrication process is the growth temperature, as this can determine the variety of substrates that could be used, especially when there is a prefabricated layer of some temperature-dependent material. The nano-wire growth temperature is determined by the eutectic temperature of the catalyst-precursor alloy ; thus, the low-temperature growth will depend on the appropriate catalysts choice. Considering the characteristics of Ga, including the Ga/Si alloy low eutectic point of 29.774°C, wide temperature range for silicon solubility and its non-reactivity to form solid compound with silicon, Ga has been suggested as a good alternative to Au to grow Si-NWs at low-temperatures. It is important to note that Ga does not act as catalyst for the decomposition of precursor gas as it does not assist the dissociation of SiH₄ below its thermal decomposition point. Therefore, Ga acts only as a solvent, and the decomposition is achieved by plasma treatment (by the use of plasma-enhanced chemical vapor deposition (PECVD) system) .

In this study, Ga catalyst is used with an aim to grow Si-NWs at a lowest temperature using PECVD technique. The growth temperature was varied between 100°C and 400°C. The grown nano-structures were characterized using scanning electron microscopy (SEM), Ultra Violet Visible spectroscopy (UV-Vis) and Ra man spectroscopy.

Electronic memory devices play a vital role in our everyday life. In the last a few decades, major progress has been observed focusing on the miniaturization of the memory size cell while increasing its density. However, materials and fabrication techniques are reaching their limits. Alternative materials and architecture of memories, as well as manufacturing processes, are considered. In order to achieve this, different types of memories such as polymer, phase change and resistance have been reported in the literature . Two-terminal non-volatile is one of the most promising memory types for fulfilling the aim of combining low cost, high density and small size devices . Therefore in this study, we present a two-terminal non-volatile memory based on Si-NWs. The suitability and potential use of Si-NWs for storage medium are investigated. The electrical behavior of these devices was examined mainly in terms of current–voltage (IV) characteristics and data retention time (current-time) measurements.

Schlocky diodes made of bulk materials do not dissipate heat quickly; hence, performance and lifespan of the device are reduced. Recently, one-dimensional (1D) nano-structures and their incorporation into Schlocky diodes have been studied extensively. Due to their high surface-to-volume ratio and space between the nano-wires, diodes made of 1D nano-structure arrays can dissipate heat faster due to individual input from each wire. Therefore, integration of these nano-materials into the device will enhance its performance and lifespan . The as-grown Si-NWs fabricated in this study were also used in a Schlocky diode, and the electrical behavior of the device is analyzed.

Solar cells fabricated with nano-wires have shown several advantages when compared to wafer-based solar cells; some of them include trapping of light, less reflection and enhanced band-gap tuning. Although these advantages do not compete to attain efficiency more than efficiencies reported until today, they help in obtaining same efficiency or less by reducing the quantity and quality of the material. Nano-wires deposited by our growth method can have a number of benefits due to their possible fabrication directly on cheaper substrates including steel, bricks, aluminum foil and conductive glass, thus reducing the price of the solar cells based on these structures. In this study, Si NW-based Schlocky solar cells were fabricated and their performance tested.

Abstract

This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapor-liquid–solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapor deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used.

The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices.

Keywords:

Silicon nano-wire; Nano-tree; Gallium; PECVD; Solar cell; Schottky diode; Bistable memory

http://www.4electron.com/phpbb/viewtopic.php?f=69&t=3286

http://uqu.edu.sa/page/ar/12486

http://www.youtube.com/watch?v=Zu6oly462_w

http://www.dbaasco.com/vb/showthread.php?t=1397 # ixzz2MEKIc2Uc

http://ar.wikipedia.org/wiki/%D8%AE%D9%84%D8%A7%D9%8A%D8%A7_%D8%A7%D9%84%D8%B3%D9%8A%D9%84%D9%8A%D9%83%D9%88%D9%86_%D8%A7%D9%84%D8%B4%D9%85%D8%B3%D9%8A%D8%A9_%D8%A8%D8%AA%D9%82%D9%86%D9%8A%D8%A9_%D8%A7%D9%84%D9%86%D8%A7%D9%86%D9%88#.D9.85.D8.B1.D8.A7.D8.AC.D8.B9

http://gehadzizo26.wix.com/nanossc

http://www.nanoscalereslett.com/content/8/1/83

    <div style="margin:10px 10px 10px 10px; padding-left:10px;text-align:left; border-left:10px solid #acacac;">
        <span style="font-size:14px; padding-bottom:5px; font-weight:bold;">Exploration of nano-element array architectures for substrate solar cells using an a-Si:H absorber</span><br/>
        <span>J. Appl. Phys. <strong>111</strong>, 123103 (2012)<br/>
        <a href="http://link.aip.org/link/doi/10.1063/1.4729539">http://dx.doi.org/10.1063/1.4729539</a></span>
    </div>

This video explains in a simplified manner how the cell works.